Verilog - Pratik's Blog

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Verilog

A collection of 2 posts

RISC V Pipelined Processor

Computer-Architecture

RISC V Pipelined Processor

In this blog post, we will explore the implementation of a pipelined RISC-V processor using Verilog, a hardware description language.

RISC V Single Cycle Processor

RISC V Single Cycle Processor

In the world of computer architecture, the single-cycle processor is a testament to simplicity and efficiency. We'll be looking at the datapath and the control unit for a single cycle processor with two classes of instructions Immediate Type Example li, r1, constant ➡️loads immediate signed value specified in